A computer's central processing unit (CPU) has a cache system called the translation lookaside buffer (TLB), which is responsible for translating physical memory into virtual memory. This a separate cache system, because it is quicker for the CPU to search this cache for memory addresses than to place it in the regular cache. To store memory addresses, the TLB uses page table entries, forming a map between virtual and physical memory addresses. When the translation lookaside buffer is used, there can either be a TLB hit or miss, meaning the memory has been found or is unknown. Computers can come with several different TLB levels to store more memory address information.
When physical memory is turned into virtual memory, creating a cache of it makes it easy for the computer to find the actual memory placement. This information can be placed in the main CPU cache, but that presents several problems. To store these data, several different access levels must be used, slowing down the entire process. A translation lookaside buffer looks around these levels and helps the CPU find the correct memory spot so the data can be opened.
The translation lookaside buffer uses a page table system that categorizes the virtual memory translation areas. When physical memory turns into virtual memory, such as when a document is stored or a program is used, the TLB stores this translation. The TLB does not store the information itself but where the memory is located, making it memory efficient.
To find a file, or anything in the memory architecture, the CPU searches through the computer. The CPU's first step is using the translation lookaside buffer to see if the memory has been cached; this produces either a hit or miss. A TLB hit means the physical memory is cached and can be found quickly. A TLB miss means the physical memory is not cached, and the CPU must look through all the page tables to find the memory, a process that is memory inefficient and takes extra time.
Most computers come with several translation lookaside buffer levels. The lowest level holds the least amount of information, but also is the quickest. When there is too much information for the first level to hold, it spills into the higher levels. These levels are not as quick but are still faster than the CPU searching through all the page tables for the physical memory address.
